FIG. 15 is a plan view showing an outline of a construction of a conventional frame transfer type solid state imager. The frame transfer type solid state imager 1 comprises; an imaging section 1i, a storage section 1s, a horizontal transfer section 1h, and an output section 1d. The imaging section 1i comprises a plurality of vertical shift registers arranged in parallel with each other in the vertical direction, and each bit of these vertical shift registers constitutes a light receiving pixel. The storage section 1s comprises a plurality of vertical shift registers which continue to the plurality of vertical shift registers which constitute the imaging section 1i. The horizontal transfer section 1h comprises a single row horizontal shift register provided on the output side of the storage section is, each bit of which is associated with a line in the plurality of vertical shift registers. The output section 1d comprises enough capacity to receive the information charges output from the horizontal transfer section 1h. 
In this construction, the information charges generated in the plurality of light receiving pixels which constitute the imaging section 1i are stored for a predetermined period in the light sensitive pixels, and are then transferred at high speed to the storage section 1s in response to a frame transfer clock φf. The information charges are then stored temporarily in the storage section 1s, and transferred sequentially line by line to the horizontal transfer section 1h in response to a vertical transfer clock φv. The information charges transferred to the horizontal transfer section 1h are then transferred to the output section 1d, sequentially pixel by pixel in response to a horizontal transfer clock φh, and converted sequentially to a voltage value and output as a picture signal Y(t).
FIG. 16 is a plan view showing a partial construction of the imaging section 1i, and FIG. 17 is a cross-sectional view along the line X-X in FIG. 16.
A P-type diffusion layer 3 which acts as the device region, is formed upon a primary surface of an N-type silicon substrate 2. A plurality of isolation regions 4 infused with high concentrations of P-type impurities are arranged in parallel a fixed distance apart in the surface region of this P-type diffusion layer 3. Between these isolation regions 4 are formed N-type diffusion layers, and a plurality of channel regions 5 which act as transfer channels for the information charges are formed. A plurality of polycrystalline silicon transfer electrodes 7 are arranged in parallel with each other on the plurality of channel regions 5 via a gate insulation film 6 made of thin silicon oxide, so as to extend in the direction transverse to the plurality of channel regions 5. Three-phase frame transfer clocks φf1 to φf3, for example, are applied to these transfer electrodes 7, and the state of the potential of the channel regions 5 is controlled by these clock pulses.
An interlayer insulating film made of the same material as the gate insulation film 6 is formed over the plurality of transfer electrodes 7, and a plurality of power supply lines 8 made of aluminum, for example, are arranged on the interlayer insulating film so as to cover the isolation regions 4. The plurality of power supply lines 8 connect to the transfer electrodes 7 via contact holes 11 formed at predetermined intervals in the interlayer insulating film, at those points where the isolation regions 4 and the transfer electrodes 7 intersect. For example, in the case of three-phase drive, a contact hole is provided for every third transfer electrode 7, and each power supply line 8 is connected to every third transfer electrode. An additional interlayer insulating film 9 is formed so as to cover the plurality of power supply lines 8, and furthermore a protective film 10 made of silicon nitride is formed over this interlayer insulating film 9.